Embodiments of the present invention relate to a method for manufacturing a highly-integrated semiconductor device, and more particularly to a method for manufacturing a semiconductor device to suppress parasitic capacitance between metal lines contained in a highly-integrated semiconductor device, such that the reliability of the semiconductor device is increased.
Generally, a semiconductor is a material that belongs to an intermediate region between a conductor and an insulator. Although the semiconductor is similar to an insulator in a pure state, electrical conductivity of the semiconductor device is increased by impurity implantation or other manipulation. The semiconductor is used to form a semiconductor device such as a transistor through impurity implantation and conductor connection. A device that has various functions simultaneously while being formed of a semiconductor element is referred to as a semiconductor device. A representative example of the semiconductor device is a semiconductor memory device. The semiconductor memory device includes a variety of constituent elements such as a transistor, a capacitor, etc. Such constituent elements are interconnected through a contact, so that electrical signals are communicated between the constituent elements. The semiconductor memory device has been rapidly developed to reduce power consumption as well as to rapidly read/write large amount of data.
As a design rule is reduced to 100 nm or less so as to increase the integration degree of the semiconductor memory device, a cross-sectional area occupied by constituent elements of the semiconductor memory device is reduced, resulting in various problems. For example, a channel length of the transistor is shortened so that a short channel effect such as a punch-through occurs. When forming a contact, an alignment error is increased so that contact resistance is also increased. As spacing between neighbor constituent elements is gradually reduced, it is difficult to electrically insulate among the constituent elements, and electrical interference caused by parasitic capacitance and the like is increased, so that operation stability and reliability of the semiconductor memory device are reduced.
In recent times, as the integration degree of the semiconductor device is increased, an active region is reduced in size. For example, in a fabrication process of 40 nm or less in an 8 F2 structure, a process for forming a device isolation region defining the active region is also becoming difficult. In addition, as the width of a gate pattern is gradually reduced, an aspect ratio of the gate pattern is increased, resulting in a defect such as an inclined part. In addition, from the viewpoint of a gate pattern, if the overlap degree is reduced because of an alignment error encountered between a recess region formed when a trench formed in an active region is buried and a pattern formed over the active region occurs, there arise various problems (for example, increase in resistance, reduction in fabrication margin for contact formation, etc.).
In addition, individual constituent elements of the semiconductor device are gradually reduced in size even in a core or peripheral region other than a cell region. It is necessary to form a contact and the like for interconnecting metal lines within a given space satisfying the design rule. In fact, as the space is gradually reduced in width, it is more difficult to form a pattern as well as to form a contact hole for forming a contact. In addition, the higher the integration degree, the smaller the spacing between neighboring lines. As a result, parasitic capacitance is unavoidably increased such that the reliability of the semiconductor device is reduced.
Meanwhile, constituent elements formed in a cell region, a core region, and a peripheral region are different in type, size, shape, and material from one another according to their use purposes. Therefore, constituent elements formed in the cell region and constituent elements formed in the core and peripheral region are not simultaneously performed, and are formed by different processes. Generally, when performing processes, such as a depositing process and an etching process, in the cell region, the cell region may be exposed using a mask that opens the cell region, and the core and peripheral region is covered with a photoresist film or the like. In contrast, when a pattern is formed in the core and peripheral region, damage to the cell region is prevented by using a mask covering the cell region. Since the pattern is formed by executing different processes in the cell region and the core and peripheral region, there arises a difference in height (i.e., a step difference) between a pattern of the cell region and a pattern of the core and peripheral region. Due to the step difference between the cell region and the core and peripheral region, it may be difficult to form a wiring for coupling constituent elements contained in the cell region to constituent elements contained in the core and peripheral region. For example, a bit line for coupling a unit cell contained in the cell region to a sense amplifier (sense-amp) formed in the core region will hereinafter be described. Under a current design rule, a size of a bit line coupled to a unit cell and a space between neighboring bit lines are very small. Therefore, provided that a step difference between the cell region and the core region is high, there is a high probability that a bit line is severed due to the high step difference.
As described above, according to the method for manufacturing conventional semiconductor devices, under a current design rule, the parasitic capacitance between metal lines is increased and the fabrication tolerances are unavoidably reduced because it is difficult to form a metal line due to a difference in height (i.e., a step difference) between the cell region and the core and peripheral region. Specifically, the increase in parasitic capacitance of a bit line for coupling a cell transistor to a sense amplifier (sense-amp) and the reduction in fabrication tolerances may have a negative influence upon the operation characteristics of the sense amplifier.